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2 kits of CMZ8GX3M2A1600C8 - Timings question


qbone2089

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I have a 2 sets of the above mentioned memory.

 

Currently i have it running 8-8-8-24-31(tRC)-2T.

 

The default tRC was 41 and i havent run into any problems yet.

 

i was just wondering if some one could tell me what effect the tRC actually has.

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tRCD:

 

Also known as RAS to CAS Delay, in addition to Column Address Strobe, there is Row Address Strobe. CAS and RAS combined allow for the exact location of memory blocks. There is an interval between RAS (activated when data is first requested) and CAS (activated when RAS is complete), as memory can't locate a block precisely in a single stage. tRCD is the cycle time between the first stage in memory access, the row strobe, and the second stage. However, the performance impact of this setting is often neglible, as memory tries to store data from programs in sequential order. It tries to keep the same row for a single program, and ordered columns to reduce the time for tRCD.

 

if you got 2 kits to play nice together at 8,8,8,24 you WIN ;):

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