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Twin XMS4000PT 2GB (pc reboot/memtest failed)


No_Fear

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recently my pc made some restarts

i did some tests with mem86+ and got the following error

test 8 ,pass 7, failing address 00011a68b1c - 282.5mb ,good ffffffff ,bad f7ffffff,err-bits 08000000

 

the settings of the ram are : 3-4-4-8 2.6v 2t

the part number i get from the cpu-z utility for each of the rams is : CMX1024-4000

 

are correct the setting i did for those ram ?

 

regards

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recently my pc made some restarts

i did some tests with mem86+ and got the following error

test 8 ,pass 7, failing address 00011a68b1c - 282.5mb ,good ffffffff ,bad f7ffffff,err-bits 08000000

 

the settings of the ram are : 3-4-4-8 2.6v 2t

the part number i get from the cpu-z utility for each of the rams is : CMX1024-4000

 

are correct the setting i did for those ram ?

 

regards

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The science behind this is quite complicated, but for most people the fastest setting is to set the tRAS to your CAS + tRCD +2. For example, if your timings were 4-4-4, the optimal tRAS would be 4 + 4 + 2 = 10. Consider tRAS as the pulse width of the strobe.

 

Research:

 

What is tRAS and why is it backwards and important at the same time?

 

The word latencies is generally used to describe a delay. However, Merriam-Webster defines the word’s origin as period of dormancy and in technical parlance, latency is often used to describe simply the duration of any event. One example is the PCI latency which describes the time any device has access to the PCI bus before it will be automatically disconnected to allow other devices access to the same resources. Why are we talking about this? Very simple, the access latencies of any device to the PCI bus are usually eight cycles, but the total latency can be set from 16-256 cycles. This shows that the same word is used to describe two entirely different parameters, the first being the time until any transactions can start, the second referring to the time that is available for transactions (minus the access latencies). As an example, a PCI latency of 32 will carry a penalty (access latency) of 8 cycles which leaves 24 cycles for actual data transfers. Therefore, decreasing this latency will not increase performance, on the contrary. The exact same is true for tRAS short for the RAS Pulse width. Historically, tRAS was defined as the time needed to establish the necessary potential between a bitline pair within the memory array until it was safe to write back the data to the memory cells of origin after a (destructive) read. Pay attention to the word read here. Memory, in many ways is like a book, you can only read after opening a book to a certain page and paragraph within that particular page. The RAS Pulse Width is the time until a page can be closed again. Therefore, just by definition, the minimum tRAS must be the RAS-to-CAS delay plus the read latency (CAS delay). That is fine for FPM and EDO memory with their single word data transfers. With SDRAM, memory controllers started to output a chain of four consecutive quadwords on every access. With DDR, that number has increased to eight quadwords that effectively are two consecutive bursts of four. Now imagine someone closes the book you are reading from in the middle of a sentence. Right in your face! And does it over and again. This is what happens if tRAS is set too short. So here is the really simple calculation: The second burst of four has at least to be initiated and prefetched into the output buffers (like you get a glimpse at the headline in a book) before you can close the page without losing all information. That means that the minimum tRAS would be tRCD+CAS latency + 2 cycles (to output the first burst of four and make way for the second burst in the output buffers). Any tRAS setting lower tRCD + CAS + 2 cycles will allow the memory controller to close the page “in your face!” over and again and that will cause a performance hit because of a truncated transfer that needs to be repeated. Along with those hassles comes the self-explanatory risk for data corruption. That one is not a real problem as long as the system is kept running but in case it is shut down and the memory content is written back to the hard disk drive, the consequences can be catastrophic. For the drive, that is.

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  • Corsair Employees
i test the modules one at a time(with the mem settings i posted above, not auto as you said to me) the first one was ok without error,but the second got :

http://xs220.xs.to/xs220/07422/memtest.jpg.xs.jpg

 

Let's get them or it replaced. Please follow the link in my signature “I think I have a bad part! Or “Tech Support Express” and we will be happy to replace them or it, please note that you are posting from the forum!

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  • 2 weeks later...

usually how long take the RMA to completed ?

 

online rma status :

Thank you for choosing Corsair products! The following is the status of your RMA Number 1031288.

RMA Issued On: 10/18/2007

Defective Parts Received on: 10/24/2007

* NOTE: it may take up to 24 hours for this date to be updated after arrival at Corsair

Part Number Received: CMX1024-4000PT

Quantity Received: 2

RMA Replacement Parts Ship Date: N/A

Replacement Part Number: N/A

Replacement Part Quantity: N/A

Replacement Shipping Method: N/A

Replacement Shipping Tracking Number: N/A

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usually how long take the RMA to completed ?

 

 

Give our customer service a call at 888-222-4346 or 510-657-8747 Ext “0” or send them an email (rmaservice@corsairmemory.com) with your RMA# and ask them for the status!

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  • Corsair Employees

You can try it and see but I would test the system with http://www.memtest.org to make sure its stable.

Command Rate is not really a memory setting and would be dependent on the make and model of MB and PSU and the specific CPU you have installed. You might look this setting up on Techarp and get a better explanation.
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