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Twinx2048-4000pt probs on DFI Lanparty

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Hi, just bought a set of twinx2048-4000PT sticks (XMS4000v1.1 0628250-1) and am having trouble reaching the rated 250mhz. Have tried changing many of the settings available on my MB and although I know my CPU can manage 3004mhz Prime95 stable (273x11), I can't even get 250mhz without memtest errors even with the CPU underclocked with 1.52v. Tried loosening timings to 3-4-4-10. Tried 2.5, 2.6, 2.7 & 2.8v but max speed is always about 243mhz.


I believe these are Samsung UCCC chips and don't like much voltage.


Any timing settings would be appreciated as my DFI Lanparty NF4 Ultra-D has about 20 options for RAM. (Also tried everything set to auto & resetting CMOS & optimized defaults).

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Contrary to popular belief, the Command rate or Command Per Clock rate is NOT a memory timing, it is a memory controller transfer characteristic.


The CPU and most types of memory have an 8 byte data transfer bus. They transfer 8 bytes of data once, twice, or four times per clock tick. However, for efficiency the basic unit of data transfer is a 32 byte "burst" of data around the address of the data the CPU needs. Any CPU reference to memory is rounded up to a complete 32 byte block. This block is transferred in a burst of 4 consecutive 8 byte transfers. Your timing settings effect this transfer, not the Command per clock.


The Command Per Clock sets the Command Rate for the memory controller. At 1T, the controller can issue commands on every clock cycle, if set to 2T the controller can only issue commands only on every other bus cycle. With DDR, the 2T command rate had some poor transferrals since there was little use for the bus interleaving (Dual Channel Mode). Let us say that if you ran at a 2.5 - 3 - 3 latency then the read command would be issued 2 cycles after an bank activate command. This would negate 1T vs 2T correct? Since the issuance was held to 2 cycles there would be no need for a single cycle command rate.


But we have DDR running in Dual Channel Mode and this mode allows for an opening of more than one page in different banks of the same memory device (slots related to dual channel ie. Bank 1 and Bank 3, etc.). So the second bank activate command that follows after the first bank activate command can not be issued since a read command for the first bank has already been scheduled. This is considered a "Bus Contention" and because of it, the next available time slot for the next bank activate command would collide with the second read command for the possibility of a page hit. This would continue until there is a no-op (no operation) return. When there is a no-op return or interval then another bank activate command can be initiated. Because of this issue, dual channel is largely useless, not only is it useless but it can even slow bank activation. This issue follows with DDR2 but one of the reasons for the creation of the DDR2 standard was to eliminate this previously mentioned bus contention. The DDR2 standard created the Posted CAS characteristic, so that there was no need to wait for the Trcd function to be completed. The Posted CAS feature allowed for the Read command to be issued immediately after the bank activate command. But this "Feature" can only be useful with a 1T command rate since a 2T command rate would eliminate the use of this characteristic.


Thus in a DDR2 system, with dual channel bank interleaving enabled there will be a more responsive system. Now there are added latancy issues with DDR2 vs DDR1 so for this benefit to be more effectively seen, one needs very low latency DDR2 DRAM.


When one compares DDR at 3 - 4 - 4 - 8 and DDR2 at 3 - 4 - 4 - 8 (Both Dual channel, bank interleaved) there becomes no doubt that the DDR2 is a far better memory transaction at 1T vs 2T and the difference at the DDR level is far less pronounced.


You will not find a great difference in realtime tests with DDR. Take a digital stopwatch and load F.E.A.R. with !T vs 2T on a DDR system. Run the F.E.A.R. benchmark and I think you will be surprised at the results.


Don't be certain that you can not effect a 1T Command rate though. Testing is the only way to be certain.


DFi boards are certainly the most finicky about ram. I had some very fine TCCD's that would not work well on my DFi Lanparty Ultra D until I finally found N4D702-1 (Samsung) and my issues were over. 290 X 10 at a 1:1 ratio and 1T. Before this BIOS I could not make past 250 with 1T. The problem is not the DRAM, it is the finicky DFI boards.





http://www.pctuner.net/forum/showthread.php?t=66649 (not english but still easily understood)

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Good luck. I heartily suggest you go to DFI Street to find others with your board. You will get some much needed help whilst you forge your way to the system speed that this board is capable of and be certain, once you get it working, you will have one fast board. :)
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Flashed to 704-2BTA. Still can't reach 250mhz, same max speed as before. Tried all RAM settings on auto (except command rate which I set to 2T) then tried fiddling with looser latencies but no good. I will try to hunt down a full set of timings to try but 1st have to wait for Ramguy to ID my chips.
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