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Unexpected tRAS & tRC


Zenefess

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Now that we're well into Autumn over here in NSW Australia I decided it was time to tighten the living s##t out of my memory modules (CMK16GX4M4B3000C15). After 2 days of tweaking/testing I reached the following timings:

http://i.imgur.com/ScW9rwa.jpg

http://i.imgur.com/XBykJIX.jpg

And here are the benchmark results:

http://i.imgur.com/2oxS9xf.jpg

 

I managed to reduce tRAS to equal tRCD, tFAW down to 4, tRC down to 8, and tREFI up to the maximum of 32,767. The third-tier timings are also a lot tighter than the X99's memory training set them to.

 

Does this seem abnormal? Is (wild guess here) the very short tRAS causing a cumulative increase/decrease in DC bias?

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