Curious about the change in timing standards between DDR3 and DDR2

[youngman]

Back in the DDR2 days, the CL timings used to be A + B + C = D. So you would see things like 4-4-4-12 or 5-5-5-15.

But now with DDR3, a lot of common timings are 9-9-9-24 instead of 9-9-9-27. And even 10-10-10-27 instead of 30. etc.

So what's the deal behind that?

Thanks.

[dta]

Hmmm. Hadn't thought of it that way, but come to think of it, that seems the "formula" for DDR2: popular (non-enthusiast) latencies for DDR2-400-3-3-3-9, DDR2-533-4-4-4-12, DDR2-667-5-5-5-15, DDR2-800-6-6-6-18.

But then for DDR1, we see (popular latencies for most types): DDR266-2-2-2-5, DDR333-2.5-3-3-7, DDR400-3-3-3-8, which doesn't fit the formula either.

[Yellowbeard]

The latencies are relative to the clock cycles. Higher frequency memory is going to apear to have higher latencies but again, it's relative. For example, DDR800 CAS 5 is roughly the same equivalent latency of DDR1600 CAS10.