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Old 05-01-2006, 02:36 PM
A_Balthazor A_Balthazor is offline
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Default DDR Clock Skew

On the Asus A8N32-SLI motherboard, there is a BIOS option for DDR clock skew. Options are Auto, and then Encrease or Decrease by 150 picoseconds (or 300, 450, etc.)

Some review sites stated that this can help in overclocking memory by adjusting the timings, but I haven't been able to find details on how exactly 'DDR Clock Skew' interacts with memory timings.

I've searched rokjat's BIOS Guide and the internet in general, no luck. Anyone know what this does?
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Old 05-02-2006, 02:13 AM
Garvin Garvin is offline
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The following link covers the timing issue in more detail:

http://www.elecdesign.com/Articles/A...9611/9611.html

Basically as the speed of the central clock increases (beats per second) the less time there is for a circuit to read a rising or falling edge of the wave form sychronously with the other circuits controlling various other functions in the mad dance of read write operation. The mismatched lengths of the traces in each of these circuits and between circuits add up to a missmatch in the exact time of a read of each of the edges of the clock signal between circuits. Phase adjusting circuits are designed to compensate in a feedback loop to overcome this difference at stock speeds but at higher than stock speeds, i.e. overclocking, the compensation in timing read differences between the rising and falling edges may no longer be perfect between circuits when set to "Auto" resulting in a slight clock skew and potential instability as the margins of read/response time from one circuit in the chain to the next fall out of synch. By including manual value settings for adjusting clock skew, one may be able to overcome the shortcomings of the "Auto" adjusting circuitry and thereby attain a higher stable overclock. In other words, while overclocking, the "Auto" adjusting circuitry may be either adding or subtracting too much or too little time to correct the clock skew. As circuits get smaller and more abundant and clock speeds go up everything making up the physical parameters of a circuit and between circuits timing-wise becomes more and more critical, even at 2/3 of the speed of light. At least that's how I read it.
__________________
temp. sig: standard RAM module timings example list, ala
4-4-4-12 =
CL-tRCD-tRP-tRAS=
CAS latency - RAS to CAS Delay - RAS Precharge - Active to Precharge Delay(also called Active Precharge delay and RAS Active time)
http://www.memtest.org/

Last edited by Garvin; 05-02-2006 at 11:39 AM.
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Old 05-02-2006, 08:46 AM
A_Balthazor A_Balthazor is offline
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Thanks, that makes sense.
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